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Ensights

Science that is transforming lives and enabling the future

Precision Engineered Techniques for Coating Plasma Chamber Components

Precision Engineered Techniques for Coating Plasma Chamber Components

Migration from 2D to 3D structures for high-density memory devices changes the nature of etching and deposition processes, especially as the number of layers for 3D NAND integration grows to 96 and beyond, and new process chemistries become commonplace. The greater number of lengthy processing steps and high aspect ratio (HAR) features involved place new demands on all steps of the chip manufacturing process, including etching, deposition, and cleaning equipment. Consistent process stability becomes harder to achieve.

  • February 3, 2021

Transitioning from Predictable to Pervasive Defectivity

Most equipment and process engineers become experts at analyzing a wafer map to quickly identify signatures indicating when their equipment or process was the perpetrator of a maverick yield event. But as defect signatures become more subtle and harder to quickly identify, there is a significant need to consider not just what in-line inspection systems are identifying, but specifically what they are not identifying. 

  • January 15, 2021

Defending Against Dangerous Electrostatic Discharge (ESD)

Much as a bolt of lightning can strike in one spot and travel, creating a path of destruction in its wake, a single electrostatic discharge can have a similar effect on a semiconductor manufacturer’s bottom line. For advanced-node manufacturers, the risk posed by electrostatic discharge has become amplified by the move to fluoropolymers, a consequence of stainless-steel process tool components failing to meet increased purity requirements.

  • September 22, 2020

Solving Defect Challenges in the EUV Process

The drive for ever more powerful microprocessors and greater memory storage places demands on all steps of the semiconductor wafer fabrication process. At some point, incremental improvements are no longer sufficient, and further device shrinking requires a completely different technology. The semiconductor industry is now experiencing this with lithography, where extreme ultraviolet (EUV) lithography is replacing 193 nm immersion (193i) lithography for more and more critical chip layers.

  • September 15, 2020

Developing Advanced Deposition Materials: A Recipe for Success

NEW PARADIGMS IN MATERIALS DEPOSITION FOR BOTH LOGIC AND MEMORY DEVICE MANUFACTURING We live in an increasingly connected world that has developed an almost unquenchable thirst for data. To process this raw data into something that is actionable requires the most advanced artificial intelligence (AI) chips for a multitude of applications, from machine learning and autonomous vehicles, to smart cities and efficient energy sources. The quest to develop these devices is driving integrated device manufacturers (IDMs) to push semiconductor manufacturing technology to its very limits.

  • August 20, 2020

Wrapping up the First Ever SEMICON West 2020 Virtual Event

Entegris recently wrapped up an exciting week at the first-ever SEMICON West virtual event. The event provided a great opportunity to connect with the community and gain valuable insight into the future of the industry.

  • August 4, 2020

Join Entegris at SEMICON West 2020 Virtual Event

Entegris is excited to celebrate the 50th anniversary of SEMI by coming together for the landmark virtual event to reaffirm our commitment to creating unique value for our customers and partners.

  • July 13, 2020

Pump it Up: Photochemical Delivery that Meets the Challenges of 3D Architectures

Photochemicals are playing an increasingly important role in bringing next generation devices to reality. While semiconductor manufacturing has always needed a pure, contamination-free environment, the requirements are tightening even further.

  • June 25, 2020

DRAM: Device Fabrication

DRAM architecture has remained virtually unchanged for the past decade, with the dimensions shrinking proportionally with each successive device node. This linear path, however, is reaching its limits for nodes below 20 nanometers (nm) including 1x, 1y, 1z, 1a, and 1b. A major change will be needed soon if DRAM is to keep up with advances in logic.

  • June 16, 2020

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