Science that is transforming lives and enabling the future
One of the longest held beliefs in semiconductor manufacturing is that yield is the single most important factor in overall wafer processing costs. Even incremental yield increases can significantly reduce manufacturing cost per wafer, or cost per square centimeter of silicon. As such, yield improvement is critical to any successful semiconductor operation. As semiconductor device nodes continue to scale, and 7 nm lines are ramping to production, this belief continues to ring true.
Shrinking feature size, advances in interconnect metals, and the need for ever tighter defectivity control all point to the growing importance of chemical mechanical planarization (CMP) to optimize fab yields. More layers of each chip require CMP to achieve planarity specifications, and contamination must be kept to a minimum.
The Fourth Industrial Revolution is surrounding us with extraordinary technologies that did not exist a few years ago. Autonomous vehicles are already being tested on public streets. Drones range from simple adolescent playthings to short- and long-range military and civilian purposes like surveying landforms, shooting movies, and delivering packages. Vast amounts of video content, created by professionals and amateurs alike, are being filmed, streamed, and stored. Surveillance, both fixed and mobile, is becoming commonplace, server farms are bigger than ever, and 4G networks are being supplemented or replaced with 5G. What all these trends have in common is that they generate enormous amounts of data that must be processed, transported, and stored faster and more reliably than ever before.
The electric vehicle (EV) market is expanding in response to customer demand, with multiple major automotive companies offering lower cost models with longer driving range.
To keep pace with the global demand and the rapid advancements in technology, the microelectronics industry depends heavily on innovating new solutions and processes to enable accelerated device production and performance. At Entegris, we are very proud to honor nearly 200 employees from our global technical community for their inventions and contributions to our intellectual property in 2020.
Migration from 2D to 3D structures for high-density memory devices changes the nature of etching and deposition processes, especially as the number of layers for 3D NAND integration grows to 96 and beyond, and new process chemistries become commonplace. The greater number of lengthy processing steps and high aspect ratio (HAR) features involved place new demands on all steps of the chip manufacturing process, including etching, deposition, and cleaning equipment. Consistent process stability becomes harder to achieve.
Most equipment and process engineers become experts at analyzing a wafer map to quickly identify signatures indicating when their equipment or process was the perpetrator of a maverick yield event. But as defect signatures become more subtle and harder to quickly identify, there is a significant need to consider not just what in-line inspection systems are identifying, but specifically what they are not identifying.
Much as a bolt of lightning can strike in one spot and travel, creating a path of destruction in its wake, a single electrostatic discharge can have a similar effect on a semiconductor manufacturer’s bottom line. For advanced-node manufacturers, the risk posed by electrostatic discharge has become amplified by the move to fluoropolymers, a consequence of stainless-steel process tool components failing to meet increased purity requirements.
The drive for ever more powerful microprocessors and greater memory storage places demands on all steps of the semiconductor wafer fabrication process. At some point, incremental improvements are no longer sufficient, and further device shrinking requires a completely different technology. The semiconductor industry is now experiencing this with lithography, where extreme ultraviolet (EUV) lithography is replacing 193 nm immersion (193i) lithography for more and more critical chip layers.